1. Field of the Invention
The present invention relates to a ferroelectric random access memory (FeRAM) having a timing reference sensing function, and more particularly to an FeRAM having a multi-bit line structure which can sense data of a common data bus by using timing of a sensing voltage of a main bit line to reach a sensing threshold voltage.
2. Description of the Background Art
In general, an FeRAM has a data processing speed equivalent to a dynamic random access memory (DRAM), preserves data even when power is off, and thus gains popularity as a next generation memory.
The FeRAM is a memory having an extremely-similar structure to the DRAM. The FeRAM employs a ferroelectric substance to form a capacitor, and thus uses high remanent polarization which is a property of the ferroelectric substance. Even if electric fields are removed, data are not deleted in the FeRAM due to the remanent polarization.
The basic structure and operation principles of the FeRAM have been disclosed in Korea Patent application No. 10-1998-14400 by the same inventors as the present invention. Therefore, detailed explanations thereof are omitted.
A cell sensing voltage decreases as a operation voltage of the FeRAM becomes lower. It is thus difficult to attain a high speed in an 1-transistor 1-capacitor (1T1C) circuit structure.
Especially when the cell data sensing voltage is low, a voltage margin for timing sensing is too small to sense the cell data. Moreover, the sensing margin may decrease by variations of the timing sensing voltage itself.